The present invention relates to the selective etching of metals and, more particularly, relates to the electrochemical etching of metals in the presence of various solders.
C4 is an advanced microelectronic chip packaging and connection technology. xe2x80x9cC4xe2x80x9d stands for Controlled Collapse Chip Connection. C4 is also known as xe2x80x9csolder bumpxe2x80x9d, xe2x80x9csolder ballsxe2x80x9d and xe2x80x9cflip chipxe2x80x9d and these terms may also be used in conjunction such as xe2x80x9cC4 solder bumpxe2x80x9d.
The basic idea of C4 is to connect chips (semiconductor devices), chip packages, or such other units by means of solder bumps between two surfaces of the units. These tiny bumps of electrically conductive solder bridge the gaps between respective pairs of metal pads on the units being connected. Each pad has a corresponding pad on the other unit""s surface; the pad arrangements are mirror images. As the units are pressed together and heated the solder bumps on the pads of the first unit are contacted with corresponding conductive pads (having no bumps) on the second unit and reflowed, partially collapsing the solder bumps and making connections between respective pads.
In C4 the solder bumps are formed directly on the metal pads of the one unit. The pads are electrically isolated from other components by the insulating substrate that surrounds each pad. The substrate might be silicon (Si) or some other material. The bottom of the pad is electrically connected into the chip circuit. major application of C4 is in joining chips to a carrier or package. Chips usually are made in rectangular arrays on a monocrystalline slab of silicon, called a xe2x80x9cwaferxe2x80x9d. Many chips are formed on each wafer, and then the wafer is broken up into individual chips and the chips are xe2x80x9cpackagedxe2x80x9d in units large enough to be handled. The C4 bumps are placed on the chips while they are still joined in a wafer.
The wafers are made as large as possible so as to reduce the number of wafers that must be processed to make a certain number of chips. For the same reason (among others) the chips are made as small as possible. Thus, the best C4 fabrication system is one that can make thousands of very small, closely-spaced solder bumps each precisely placed over a large area.
C4 solder bumps must be mechanically well-fastened to their pads, or they may be torn off when the two surfaces are pushed together. It will be appreciated that a complex device such as a computer may have dozens of chips and hundreds or thousands of C4 solder ball connections, and the entire device may be rendered useless if only one of the bumps fails. The attachment of the C4 bumps requires careful design.
One method of forming solder bumps uses sputtering or vacuum deposition. In this method, solder metal is evaporated in a vacuum chamber. The metal vapor coats everything in the chamber with a thin film of the evaporated metal. To form solder bumps on the substrate, the vapor is allowed to pass through holes in a metal mask held over the substrate. The solder vapor passing through the holes condenses onto the cool surface into solder bumps. This method requires a high vacuum chamber to hold the substrate, mask, and flash evaporator.
An alternative technique for making solder bumps is electrodeposition, also called electrochemical plating or electroplating. This method also uses a mask and forms solder bumps only at the selected sites, but the technique is very different from the evaporation method.
The first step in electrolytically forming C4 solder bumps is to deposit a continuous stack of metal films across the wafer to be bumped. This so-called xe2x80x9cseed layerxe2x80x9d performs a dual function. First, it provides a conductive path for current flow during the electrolytic deposition of the solder bumps. Second, it remains under the solder bumps and forms the basis for the ball limiting metallurgy (BLM) for the C4s. Therefore, it must contain at least one layer that is conductive enough to permit uniform electrodeposition across the entire expanse of the wafer. The bottom layer must adhere well to the underlying semiconductor device passivation and the top layer must interact sufficiently with the solder to form a reliable bond. In addition, the BLM may contain barrier layers which prevent the solder from detrimentally interacting with the underlying device constituents. Finally, the stresses generated by the composite stack should be low enough to sustain the reliability of the C4 joint throughout various thermal and mechanical stresses. Considering all of these factors, seed layers often consist of more than one metal layer, and these various layers must be etched away from between the C4s at some point during the processing in order to electrically isolate the interconnects.
The second step, after the seed layer is laid down, is to form a mask by photolithography. A layer of photoresist is laid onto the seed layer and exposed to light. Unexposed photoresist (if a negative photoresist) can then be washed away to leave the cured photoresist behind as a mask. The mask has rows of holes where the solder bumps are to be deposited.
The third step is electrodeposition (electroplating) of solder into the mask holes.
After the solder bumps are formed, the mask of cured photoresist is removed. The substrate now is covered with the continuous seed layer and numerous solder bumps. Then, the seed layer is removed in between the solder bumps to electrically isolate them by suitable wet etching and/or electroetching processes.
The solder typically used for the C4 solder bumps is 97 weight percent Pb and 3 weight percent Sn. A typical seed layer would comprise a TiW layer, a phased Cr/Cu layer or a Cr/Cu alloy and a Cu layer. The process utilized to simultaneously remove the Cr/Cu and Cu layers is an electroetching process which includes an aqueous solution containing glycerol and potassium sulfate as disclosed in Datta et al. U.S. Pat. No. 5,486,282, the disclosure of which is incorporated by reference herein. The glycerol serves as a wetting agent, but the purpose of the potassium sulfate is twofold. First, the potassium sulfate imparts electrolytic conductivity to the solution. Second, the free sulfate ions complex readily with the high Pb solder bumps and form a protective crust which prevents the solder bumps from being dissolved during the electroetching process. The TiW layer is then etched using a wet etching process which includes an aqueous etchant comprising hydrogen peroxide, EDTA and potassium sulfate as disclosed in Datta et al. U.S. Pat. No. 5,462,638 and Fanti et al. U.S. Pat. No. 6,015,505, the disclosures of which are incorporated by reference herein. The xe2x80x9ccrustxe2x80x9d on the solder bumps is removed in a subsequent cleaning process.
More recent applications use a lower melting solder for the C4 bumps to enable lower temperature chip joining. Such a lower melting solder could be the lead/tin solder composition comprising 63 weight percent Sn and 37 weight percent Pb.
Cotte et al. U.S. Pat. No. 5,800,726, the disclosure of which is incorporated by reference herein, have proposed an aqueous solution for the wet etching of various metals, such as TiW, in the presence of eutectic solder. This solution comprises potassium phosphate, hydrogen peroxide, EDTA and oxalic acid.
The present inventors have recognized that the current electroetch process is not effective with respect to high Sn solder bumps. The reason is that Sn is not very reactive with sulfate ions so the prior art electroetch solution as disclosed in the above Datta et al. U.S. Pat. No. 5,486,282 does not form a protective crust over the solder bump during electroetch. The undesirable result is that a large amount of the Sn is leached out from the solder bump. In addition, the dissolved Sn is free to redeposit on the TiW and complex with the TiW so as to render the TiW layer impermeable to traditional wet etching.
The problem is further complicated by hierarchical solder structures in which, for example, a low melting, high Sn solder bump is deposited over a high melting, high Pb solder bump.
The present inventors have thus recognized a need to be able to effectively electroetch metals and not affect the solder bumps where at least a portion of the solder bump contains a high Sn solder.
Accordingly, it is a purpose of the present invention to electroetch substrates having metals to be electroetched and high Sn solder bumps which are not to be etched.
It is a further purpose of the present invention to electroetch substrates having metals to be electroetched and solder hierarchies containing high Sn solder bumps and high lead solder bumps which are not to be etched.
These and other purposes of the present invention will become more apparent from the following description considered in conjunction with the accompanying drawings.
The purposes of the invention have been achieved by providing according to a first aspect of the invention an aqueous electrochemical etchant for etching metals in the presence of one or more metals not to be etched, the etchant comprising:
glycerol in the concentration range of 1.30 to 1.70 M;
a sulfate compound having a sulfate ion concentration in the range of 0 to 0.5 M; and
a phosphate compound having a phosphate ion concentration in the range of 0.1 to 0.5 M.
According to a second aspect of the invention, there is provided a method for selectively dissolving, in an article, one or more metals to be dissolved in the presence of one or more metals not to be dissolved, the method comprising the step of:
electrochemically etching the metals to be dissolved with an aqueous etchant comprising glycerol in the concentration range of 1.30 to 1.70 M, a sulfate compound having a sulfate ion concentration in the range of 0 to 0.5 M, and a phosphate compound having a phosphate ion concentration in the range of 0.1 to 0.5 M.
According to a third aspect of the invention, there is provided a method for selectively etching an article, the method comprising the steps of:
providing an article having one or more metals to be dissolved in the presence of one or more metals not to be dissolved; and
electrochemically etching the one or more metals to be dissolved with an aqueous etchant comprising glycerol in the concentration range of 1.30 to 1.70 M, a sulfate compound having a sulfate ion concentration in the range of 0 to 0.5 M, and a phosphate compound having a phosphate ion concentration in the range of 0.1 to 0.5 M.